00001
00021 #ifndef __ANALOGY_NI_MITE_H__
00022 #define __ANALOGY_NI_MITE_H__
00023
00024 #include <linux/pci.h>
00025
00026 #include <analogy/analogy_driver.h>
00027
00028 #define PCI_VENDOR_ID_NATINST 0x1093
00029 #define PCI_MITE_SIZE 4096
00030 #define PCI_DAQ_SIZE 4096
00031 #define PCI_DAQ_SIZE_660X 8192
00032 #define PCIMIO_COMPAT
00033 #define MAX_MITE_DMA_CHANNELS 8
00034
00035 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
00036
00037 struct mite_dma_descriptor {
00038 u32 count;
00039 u32 addr;
00040 u32 next;
00041 u32 dar;
00042 };
00043
00044 struct mite_dma_descriptor_ring {
00045 struct pci_dev *pcidev;
00046 u32 n_links;
00047 struct mite_dma_descriptor *descriptors;
00048 dma_addr_t descriptors_dma_addr;
00049 };
00050
00051 struct mite_channel {
00052 struct mite_struct *mite;
00053 u32 channel;
00054 u32 dir;
00055 u32 done;
00056 struct mite_dma_descriptor_ring *ring;
00057 };
00058
00059 struct mite_struct {
00060 struct list_head list;
00061 a4l_lock_t lock;
00062 u32 used;
00063 u32 num_channels;
00064
00065 struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
00066 u32 channel_allocated[MAX_MITE_DMA_CHANNELS];
00067
00068 struct pci_dev *pcidev;
00069 resource_size_t mite_phys_addr;
00070 void *mite_io_addr;
00071 resource_size_t daq_phys_addr;
00072 void *daq_io_addr;
00073 };
00074
00075 static inline
00076 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
00077 {
00078 struct mite_dma_descriptor_ring *ring =
00079 kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_DMA);
00080
00081 if (ring == NULL)
00082 return ring;
00083
00084 memset(ring, 0, sizeof(struct mite_dma_descriptor_ring));
00085
00086 ring->pcidev = mite->pcidev;
00087 if (ring->pcidev == NULL) {
00088 kfree(ring);
00089 return NULL;
00090 }
00091
00092 return ring;
00093 };
00094
00095 static inline void mite_free_ring(struct mite_dma_descriptor_ring *ring)
00096 {
00097 if (ring) {
00098 if (ring->descriptors) {
00099 pci_free_consistent(
00100 ring->pcidev,
00101 ring->n_links *
00102 sizeof(struct mite_dma_descriptor),
00103 ring->descriptors, ring->descriptors_dma_addr);
00104 }
00105 kfree(ring);
00106 }
00107 };
00108
00109 static inline unsigned int mite_irq(struct mite_struct *mite)
00110 {
00111 return mite->pcidev->irq;
00112 };
00113 static inline unsigned int mite_device_id(struct mite_struct *mite)
00114 {
00115 return mite->pcidev->device;
00116 };
00117
00118 int a4l_mite_setup(struct mite_struct *mite, int use_iodwbsr_1);
00119 void a4l_mite_unsetup(struct mite_struct *mite);
00120 void a4l_mite_list_devices(void);
00121 struct mite_struct * a4l_mite_find_device(int bus,
00122 int slot, unsigned short device_id);
00123 struct mite_channel *
00124 a4l_mite_request_channel_in_range(struct mite_struct *mite,
00125 struct mite_dma_descriptor_ring *ring,
00126 unsigned min_channel, unsigned max_channel);
00127 static inline struct mite_channel *mite_request_channel(struct mite_struct
00128 *mite, struct mite_dma_descriptor_ring *ring)
00129 {
00130 return a4l_mite_request_channel_in_range(mite, ring, 0,
00131 mite->num_channels - 1);
00132 }
00133 void a4l_mite_release_channel(struct mite_channel *mite_chan);
00134
00135 void a4l_mite_dma_arm(struct mite_channel *mite_chan);
00136 void a4l_mite_dma_disarm(struct mite_channel *mite_chan);
00137 int a4l_mite_sync_input_dma(struct mite_channel *mite_chan, a4l_subd_t *subd);
00138 int a4l_mite_sync_output_dma(struct mite_channel *mite_chan, a4l_subd_t *subd);
00139 u32 a4l_mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
00140 u32 a4l_mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
00141 u32 a4l_mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
00142 u32 a4l_mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
00143 u32 a4l_mite_bytes_in_transit(struct mite_channel *mite_chan);
00144 u32 a4l_mite_get_status(struct mite_channel *mite_chan);
00145 int a4l_mite_done(struct mite_channel *mite_chan);
00146 void a4l_mite_prep_dma(struct mite_channel *mite_chan,
00147 unsigned int num_device_bits, unsigned int num_memory_bits);
00148 int a4l_mite_buf_change(struct mite_dma_descriptor_ring *ring, a4l_subd_t *subd);
00149
00150 #ifdef CONFIG_DEBUG_MITE
00151 void mite_print_chsr(unsigned int chsr);
00152 void a4l_mite_dump_regs(struct mite_channel *mite_chan);
00153 #endif
00154
00155 static inline int CHAN_OFFSET(int channel)
00156 {
00157 return 0x500 + 0x100 * channel;
00158 };
00159
00160 enum mite_registers {
00161
00162
00163
00164 MITE_UNKNOWN_DMA_BURST_REG = 0x28,
00165 MITE_IODWBSR = 0xc0,
00166 MITE_IODWBSR_1 = 0xc4,
00167 MITE_IODWCR_1 = 0xf4,
00168 MITE_PCI_CONFIG_OFFSET = 0x300,
00169 MITE_CSIGR = 0x460
00170 };
00171 static inline int MITE_CHOR(int channel)
00172 {
00173 return CHAN_OFFSET(channel) + 0x0;
00174 };
00175 static inline int MITE_CHCR(int channel)
00176 {
00177 return CHAN_OFFSET(channel) + 0x4;
00178 };
00179 static inline int MITE_TCR(int channel)
00180 {
00181 return CHAN_OFFSET(channel) + 0x8;
00182 };
00183 static inline int MITE_MCR(int channel)
00184 {
00185 return CHAN_OFFSET(channel) + 0xc;
00186 };
00187 static inline int MITE_MAR(int channel)
00188 {
00189 return CHAN_OFFSET(channel) + 0x10;
00190 };
00191 static inline int MITE_DCR(int channel)
00192 {
00193 return CHAN_OFFSET(channel) + 0x14;
00194 };
00195 static inline int MITE_DAR(int channel)
00196 {
00197 return CHAN_OFFSET(channel) + 0x18;
00198 };
00199 static inline int MITE_LKCR(int channel)
00200 {
00201 return CHAN_OFFSET(channel) + 0x1c;
00202 };
00203 static inline int MITE_LKAR(int channel)
00204 {
00205 return CHAN_OFFSET(channel) + 0x20;
00206 };
00207 static inline int MITE_LLKAR(int channel)
00208 {
00209 return CHAN_OFFSET(channel) + 0x24;
00210 };
00211 static inline int MITE_BAR(int channel)
00212 {
00213 return CHAN_OFFSET(channel) + 0x28;
00214 };
00215 static inline int MITE_BCR(int channel)
00216 {
00217 return CHAN_OFFSET(channel) + 0x2c;
00218 };
00219 static inline int MITE_SAR(int channel)
00220 {
00221 return CHAN_OFFSET(channel) + 0x30;
00222 };
00223 static inline int MITE_WSCR(int channel)
00224 {
00225 return CHAN_OFFSET(channel) + 0x34;
00226 };
00227 static inline int MITE_WSER(int channel)
00228 {
00229 return CHAN_OFFSET(channel) + 0x38;
00230 };
00231 static inline int MITE_CHSR(int channel)
00232 {
00233 return CHAN_OFFSET(channel) + 0x3c;
00234 };
00235 static inline int MITE_FCR(int channel)
00236 {
00237 return CHAN_OFFSET(channel) + 0x40;
00238 };
00239
00240 enum MITE_IODWBSR_bits {
00241 WENAB = 0x80,
00242 };
00243
00244 static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
00245 {
00246 unsigned order = 0;
00247 while (size >>= 1)
00248 ++order;
00249 BUG_ON(order < 1);
00250 return (order - 1) & 0x1f;
00251 }
00252
00253 enum MITE_UNKNOWN_DMA_BURST_bits {
00254 UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
00255 };
00256
00257 static inline int mite_csigr_version(u32 csigr_bits)
00258 {
00259 return csigr_bits & 0xf;
00260 };
00261 static inline int mite_csigr_type(u32 csigr_bits)
00262 {
00263 return (csigr_bits >> 4) & 0xf;
00264 };
00265 static inline int mite_csigr_mmode(u32 csigr_bits)
00266 {
00267 return (csigr_bits >> 8) & 0x3;
00268 };
00269 static inline int mite_csigr_imode(u32 csigr_bits)
00270 {
00271 return (csigr_bits >> 12) & 0x3;
00272 };
00273 static inline int mite_csigr_dmac(u32 csigr_bits)
00274 {
00275 return (csigr_bits >> 16) & 0xf;
00276 };
00277 static inline int mite_csigr_wpdep(u32 csigr_bits)
00278 {
00279 unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
00280 if (wpdep_bits == 0)
00281 return 0;
00282 else
00283 return 1 << (wpdep_bits - 1);
00284 };
00285 static inline int mite_csigr_wins(u32 csigr_bits)
00286 {
00287 return (csigr_bits >> 24) & 0x1f;
00288 };
00289 static inline int mite_csigr_iowins(u32 csigr_bits)
00290 {
00291 return (csigr_bits >> 29) & 0x7;
00292 };
00293
00294 enum MITE_MCR_bits {
00295 MCRPON = 0,
00296 };
00297
00298 enum MITE_DCR_bits {
00299 DCR_NORMAL = (1 << 29),
00300 DCRPON = 0,
00301 };
00302
00303 enum MITE_CHOR_bits {
00304 CHOR_DMARESET = (1 << 31),
00305 CHOR_SET_SEND_TC = (1 << 11),
00306 CHOR_CLR_SEND_TC = (1 << 10),
00307 CHOR_SET_LPAUSE = (1 << 9),
00308 CHOR_CLR_LPAUSE = (1 << 8),
00309 CHOR_CLRDONE = (1 << 7),
00310 CHOR_CLRRB = (1 << 6),
00311 CHOR_CLRLC = (1 << 5),
00312 CHOR_FRESET = (1 << 4),
00313 CHOR_ABORT = (1 << 3),
00314 CHOR_STOP = (1 << 2),
00315 CHOR_CONT = (1 << 1),
00316 CHOR_START = (1 << 0),
00317 CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
00318 };
00319
00320 enum MITE_CHCR_bits {
00321 CHCR_SET_DMA_IE = (1 << 31),
00322 CHCR_CLR_DMA_IE = (1 << 30),
00323 CHCR_SET_LINKP_IE = (1 << 29),
00324 CHCR_CLR_LINKP_IE = (1 << 28),
00325 CHCR_SET_SAR_IE = (1 << 27),
00326 CHCR_CLR_SAR_IE = (1 << 26),
00327 CHCR_SET_DONE_IE = (1 << 25),
00328 CHCR_CLR_DONE_IE = (1 << 24),
00329 CHCR_SET_MRDY_IE = (1 << 23),
00330 CHCR_CLR_MRDY_IE = (1 << 22),
00331 CHCR_SET_DRDY_IE = (1 << 21),
00332 CHCR_CLR_DRDY_IE = (1 << 20),
00333 CHCR_SET_LC_IE = (1 << 19),
00334 CHCR_CLR_LC_IE = (1 << 18),
00335 CHCR_SET_CONT_RB_IE = (1 << 17),
00336 CHCR_CLR_CONT_RB_IE = (1 << 16),
00337 CHCR_FIFODIS = (1 << 15),
00338 CHCR_FIFO_ON = 0,
00339 CHCR_BURSTEN = (1 << 14),
00340 CHCR_NO_BURSTEN = 0,
00341 CHCR_BYTE_SWAP_DEVICE = (1 << 6),
00342 CHCR_BYTE_SWAP_MEMORY = (1 << 4),
00343 CHCR_DIR = (1 << 3),
00344 CHCR_DEV_TO_MEM = CHCR_DIR,
00345 CHCR_MEM_TO_DEV = 0,
00346 CHCR_NORMAL = (0 << 0),
00347 CHCR_CONTINUE = (1 << 0),
00348 CHCR_RINGBUFF = (2 << 0),
00349 CHCR_LINKSHORT = (4 << 0),
00350 CHCR_LINKLONG = (5 << 0),
00351 CHCRPON =
00352 (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
00353 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
00354 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
00355 };
00356
00357 enum ConfigRegister_bits {
00358 CR_REQS_MASK = 0x7 << 16,
00359 CR_ASEQDONT = 0x0 << 10,
00360 CR_ASEQUP = 0x1 << 10,
00361 CR_ASEQDOWN = 0x2 << 10,
00362 CR_ASEQ_MASK = 0x3 << 10,
00363 CR_PSIZE8 = (1 << 8),
00364 CR_PSIZE16 = (2 << 8),
00365 CR_PSIZE32 = (3 << 8),
00366 CR_PORTCPU = (0 << 6),
00367 CR_PORTIO = (1 << 6),
00368 CR_PORTVXI = (2 << 6),
00369 CR_PORTMXI = (3 << 6),
00370 CR_AMDEVICE = (1 << 0),
00371 };
00372 static inline int CR_REQS(int source)
00373 {
00374 return (source & 0x7) << 16;
00375 };
00376 static inline int CR_REQSDRQ(unsigned drq_line)
00377 {
00378
00379
00380 return CR_REQS((drq_line & 0x3) | 0x4);
00381 }
00382 static inline int CR_RL(unsigned int retry_limit)
00383 {
00384 int value = 0;
00385
00386 while (retry_limit) {
00387 retry_limit >>= 1;
00388 value++;
00389 }
00390 if (value > 0x7)
00391 __a4l_err("bug! retry_limit too large\n");
00392
00393 return (value & 0x7) << 21;
00394 }
00395
00396 enum CHSR_bits {
00397 CHSR_INT = (1 << 31),
00398 CHSR_LPAUSES = (1 << 29),
00399 CHSR_SARS = (1 << 27),
00400 CHSR_DONE = (1 << 25),
00401 CHSR_MRDY = (1 << 23),
00402 CHSR_DRDY = (1 << 21),
00403 CHSR_LINKC = (1 << 19),
00404 CHSR_CONTS_RB = (1 << 17),
00405 CHSR_ERROR = (1 << 15),
00406 CHSR_SABORT = (1 << 14),
00407 CHSR_HABORT = (1 << 13),
00408 CHSR_STOPS = (1 << 12),
00409 CHSR_OPERR_mask = (3 << 10),
00410 CHSR_OPERR_NOERROR = (0 << 10),
00411 CHSR_OPERR_FIFOERROR = (1 << 10),
00412 CHSR_OPERR_LINKERROR = (1 << 10),
00413 CHSR_XFERR = (1 << 9),
00414 CHSR_END = (1 << 8),
00415 CHSR_DRQ1 = (1 << 7),
00416 CHSR_DRQ0 = (1 << 6),
00417 CHSR_LxERR_mask = (3 << 4),
00418 CHSR_LBERR = (1 << 4),
00419 CHSR_LRERR = (2 << 4),
00420 CHSR_LOERR = (3 << 4),
00421 CHSR_MxERR_mask = (3 << 2),
00422 CHSR_MBERR = (1 << 2),
00423 CHSR_MRERR = (2 << 2),
00424 CHSR_MOERR = (3 << 2),
00425 CHSR_DxERR_mask = (3 << 0),
00426 CHSR_DBERR = (1 << 0),
00427 CHSR_DRERR = (2 << 0),
00428 CHSR_DOERR = (3 << 0),
00429 };
00430
00431 static inline void mite_dma_reset(struct mite_channel *mite_chan)
00432 {
00433 writel(CHOR_DMARESET | CHOR_FRESET,
00434 mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
00435 };
00436
00437 #endif